1. Field of the Invention
The present invention relates to a gate driver for a display device, and more particularly, to a reliable gate driver and a method of driving the gate driver.
2. Background of the Related Art
Display devices having a screen to display an image by controlling pixels arranged in a matrix have been widely used. Examples of the display devices include a liquid crystal display device (LCD) and an organic light emitting diode device (OLED). Such display devices have a display panel having pixels arranged in a matrix, a gate driver for scanning pixels line by line, and a data driver for supplying an image data.
Recently, a display device having a gate driver and/or a data driver embedded on a display panel has been actively developed to simplify the fabricating process, reduce the weight and size of the panel, and reduce manufacturing cost. When manufacturing the display panel, the gate diver and/or the data driver are/is manufactured simultaneously. A plurality of thin film transistors (TFTs) are provided to control each of the pixels in the display panel, and the gate driver and/or the data driver can be manufactured through the same semiconductor process as the TFT.
Each of the gate drivers includes a plurality of shift registers for outputting output signals. For example, when the display panel has ten gate lines, ten shift registers are provided to supply their output signals to the ten gate lines, respectively.
FIG. 1 is a block diagram of a related art gate driver. As shown in FIG. 1, the related art gate driver includes a plurality of shift registers SRC1 through SRC[N+1] connected in a cascade manner. An output terminal OUT of each shift register is connected to a set terminal SET of the next shift register. The shift registers include n number of shift registers SRC1 through SRC[N] corresponding to n number of gate lines, and a dummy shift register SRC[N+1] for resetting the last shift register SRC[N].
The first shift register SRC1 is set by a pulse start signal STV. The pulse start signal is a pulse synchronized with a vertical synch signal Vsync. Each of the shift registers SRC2 through SRC[N+1] is set by an output signal of its previous shift register. When there are n number of the gate lines, output signals GOUT1 through GOUT[N] of the shift registers are connected to the corresponding gate lines, and an output signal GOUT[N+1] of the dummy shift register SRC[N+1] is not connected to any gate line.
A first clock CKV is supplied to the odd-numbered shift registers SRC1, SRC3, and so on, and a second clock CKVB is supplied to the even-numbered shift registers SRC2, SRC4, and so on. A phase of the first clock CKV is opposite to that of the second clock CKVB. The first clock CKV is simultaneously applied to the odd-numbered shift registers SRC1, SRC3, and so on, and the second clock CKVB is simultaneously applied to the even-numbered shift registers SRC2, SRC4, and so on.
The pulse start signal STV is applied to the first shift register SRC1 when the second clock CKVB is high. And, the shift registers SRC1 through SRC[N] output the respective output signals GOUT1 through GOUT[N] in synchronization with the first clock CKV or the second clock CKVB. Each of the shift registers SRC1 through SRC[N] is reset by the output signal of its next shift register.
Accordingly, each of the shift registers SRC1 through SRC[N] is set by the output signal of its previous shift register, outputs the output signal in synchronization with the first or second clocks CKV or CKVB, and then is reset by the output signal of its next shift register. However, since there is no shift register next to the dummy shift register SRC[N+1], the dummy shift register SRC[N+1] is reset by its own output signal GOUT[N+1].
FIG. 2 is a circuit diagram of a first shift register SRC1 illustrated in FIG. 1. FIG. 3 is a waveform diagram of driving signals applied to the first shift register of FIG. 2. Since all the shift registers illustrated in FIG. 1 have the identical structure to one another, only the first shift register SRC1 will be described for convenience.
When the pulse start signal STV is high, the first clock CKV and the second clock CKVB are low and high, respectively. Also, the first clock CKV and the second clock CKVB have a high state in clock unit. As shown in FIGS. 2 and 3, the first shift register SRC1 is set by the pulse start signal STV of a high state during a second clock (CKVB) period (i.e., when the second clock CKVB is high). That is, when the pulse start signal STV is applied, a Q node is charged to a voltage of the pulse start signal STV. A first transistor M1 is turned on by the charged Q node. Then, a QB node is discharged by a voltage difference (VDD-VSS) between a first power supply voltage and a second power supply voltage. Consequently, a low voltage of the QB node is maintained by a ratio of a resistance R1 of a first transistor M1 to a resistance R6 of a sixth transistor M6.
During a first clock (CKV) period (i.e., when the first clock signal CKV is high), a first output signal GOUT1 is output in response to the first clock CKV. When the first clock CKV is applied to the second transistor M2, a bootstrapping is caused by a drain-gate capacitance Cgd in a second transistor M2, and thus the Q node is charged with a voltage higher than that of the charged pulse start signal STV. Accordingly, the second transistor M2 is turned on and thus the first clock CKV is output as the first output signal GOUT1.
During the subsequent second clock (CKVB) period, the first shift register SRC1 is reset by the second output signal GOUT2 of its next shift register SRC2. That is, when a fifth transistor M5 is turned on by the second output signal GOUT2 of the shift register SRC2, the Q node is discharged by a first power supply voltage VSS passing through the fifth transistor M5. Additionally, the first transistor M1 is turned off by the discharged Q node, and the QB node is charged with the second supply voltage VDD passing through the sixth transistor M6, so that third and fourth transistors M3 and M4 are turned on by the charged QB node. Accordingly, the Q node is easily discharged by the first supply the voltage VSS passing through the turned-on fourth transistor M4. In this case, most of the output signal GOUT1 is discharged through a source-drain path of the second transistor M2, and the remaining output signal GOUT1 is discharged through the first power supply voltage VSS by the turned-on third transistor M3.
Since the other shift registers SRC2 through SRC[N] operate in the same way as the first shift register SRC1, the output signals GOUT1 through GOUT[N] having a high state are output sequentially. Accordingly, the output signals GOUT1 through GOUT[N] having a high state are sequentially output during one frame period by the shift registers SRC1 through SRC[N]. Then, these processes are repeated frame period by frame period.
During one frame period (16.67 ms), a high-state voltage is output for a very short time (20 μs) and a low-state voltage is output for the remaining time (90% or more) from each of the shift registers SRC1 through SRC[N]. In this case, a high-state voltage is maintained at the QB node connected to the gate of the third transistor M3 while the low-state voltage is output.
Consequently, the high-state voltage is maintained at the QB node for most of the frame period. Therefore, when the above operation is repeated for each frame period, a stress voltage is accumulated in the third transistor M3 connected to the QB node, thereby degrading the third transistor. For example, the stress voltage is accumulated over the frame periods as illustrated in FIG. 4.
Generally, an LCD is used as a display device and expected to operate for a number of years. In this case, the continuously cumulative stress voltage greatly degrades the threshold voltage and carrier mobility of the third transistor M3. Consequently, the third transistor M3 suffers in performance, making it difficult to accurately control the operation of the third transistor M3. Accordingly, an image is abnormally displayed on the LCD screen. Moreover, the performance degradation of the third transistor M3 also reduces the lifetime of the LCD.